VHDL Compiler Hack 2.0.2 + Redeem Codes
Learn and code in VHDL
Developer: Ketan Appa
Category: Education
Price: Free
Version: 2.0.2
ID: com.kappsmart.vhdlcompiler
Screenshots
Description
Write VHDL code directly on your iPhone, iPad and iPod Touch! This app is ideal for learning and testing code snippets!
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
This app uses the open-source GHDL simulator (http://ghdl.free.fr). GHDL is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is not a synthesis tool: you cannot create a netlist with GHDL (yet).
Features:
- Compile and run your program
- View program output or detailed error
- Custom keyboard for easy input of frequently used characters
- Optimized for connecting with external physical/bluetooth keyboard
- Advanced source code editor with syntax highlighting and line numbers
- Open, save, import and share VHDL files.
Limitations:
- Internet connection is required for compilation
- Maximum program running time is 20s
- All entities should be have the same name as their files.
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
This app uses the open-source GHDL simulator (http://ghdl.free.fr). GHDL is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is not a synthesis tool: you cannot create a netlist with GHDL (yet).
Features:
- Compile and run your program
- View program output or detailed error
- Custom keyboard for easy input of frequently used characters
- Optimized for connecting with external physical/bluetooth keyboard
- Advanced source code editor with syntax highlighting and line numbers
- Open, save, import and share VHDL files.
Limitations:
- Internet connection is required for compilation
- Maximum program running time is 20s
- All entities should be have the same name as their files.
Version history
2.0.2
2023-08-21
Bug fixes and performance improvement
2.0.1
2022-12-26
Bug fixes and performance improvement
2.0
2022-11-24
Optimized for iOS and iPadOS 16
1.9
2022-06-09
Optimized for iOS and iPadOS 15
1.8
2021-01-15
Bug fixes and performance improvement
1.7.2
2020-10-15
Bug fixes and performance improvement
1.7.1
2020-09-29
Fixed a bug when pasting text
1.7
2020-09-19
Optimized for iOS and iPadOS 14
1.6
2020-05-21
Bug fixes for exporting files in iPad
1.4
2020-03-16
New Settings UI
1.3
2020-01-17
Optimized for iOS 13
1.2.2
2019-10-09
Improved connectivity
1.2.1
2019-07-10
Enable/disable syntax highlighting in Settings
1.2
2019-07-01
Improved connectivity
1.1.2
2019-06-14
Auto indentation and bracket completion can be changed in Settings
1.1.1
2019-05-11
Word wrap output
1.1
2019-05-03
Find and replace text
1.0
2019-04-27
Cheat Codes for In-App Purchases
| Item | Price | iPhone/iPad | Android |
|---|---|---|---|
| Upgrade (Upgrade to premium version) |
Free |
JI561596944✱✱✱✱✱ | C364771✱✱✱✱✱ |
Ways to hack VHDL Compiler
- Redeem codes (Get the Redeem codes)
Download hacked APK
Download VHDL Compiler MOD APK
Request a Hack
Ratings
2.6 out of 5
5 Ratings
Reviews
Tdurrer,
Works great simulates std_logic circuits just fine
I realized that it’s essential to limit simulation with ultimately a WAIT; statement including a clock generator with limited total time
Here is a simple test setup beyond just text:
Enjoy.. great job by the developer of the App and the original open source VHDL Compiler Designer
————————————————
-- Hello world program
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all; -- Imports the standard textio package.
-- Defines a design entity, without any ports.
entity hello is
end hello;
architecture behaviour of hello is
signal index : integer:=0;
signal clk : std_logic := '0';
begin
process(clk)
variable l : line;
begin
if(rising_edge(clk)) then
write(l,String'("/"));
writeline (output, l);
end if;
end process; process
begin
index <= index +1;
clk <= not clk;
wait for 1 ns;
if index > 20 then
wait;
end if;
end process;
end behaviour;
Here is a simple test setup beyond just text:
Enjoy.. great job by the developer of the App and the original open source VHDL Compiler Designer
————————————————
-- Hello world program
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all; -- Imports the standard textio package.
-- Defines a design entity, without any ports.
entity hello is
end hello;
architecture behaviour of hello is
signal index : integer:=0;
signal clk : std_logic := '0';
begin
process(clk)
variable l : line;
begin
if(rising_edge(clk)) then
write(l,String'("/"));
writeline (output, l);
end if;
end process; process
begin
index <= index +1;
clk <= not clk;
wait for 1 ns;
if index > 20 then
wait;
end if;
end process;
end behaviour;
